module test_states(clk, rst, o1, o2, o3, o4);
input clk, rst;

//outputs for SSD
output [6:0]o1;
output [6:0]o2;
output [6:0]o3;
output [6:0]o4;

reg [6:0]o1;
reg [6:0]o2;
reg [6:0]o3;
reg [6:0]o4;

reg [2:0] state;
reg [2:0] nextState;

parameter start  =3'd0;
parameter a_b = 3'd1;
parameter b_c = 3'd2;
parameter c_d = 3'd3;
parameter finish = 3'd4;

reg [1:0] count;

reg [3:0] outA;
reg [3:0] outB;
reg [3:0] outC;
reg [3:0] outD;

//state update
always @ (posedge clk)
begin//begin always
	if (rst == 1'b1)
	begin//if
		state <= start;
	end//if	
	else
	begin//else
		state <= nextState;
	end//else
end//end always

//calculate nextState
always @ (*)
begin//being always

	case(state)
 
start:	begin//start state
				nextState = a_b;
			end//start state
 
 a_b:		begin// a_b state
			
				nextState = b_c;
			end//a_b state

	
	b_c:	begin//state b_c
						
					nextState = c_d;
				end//state b_c
	
	c_d:		begin//state c_d
		
						nextState = finish;
		
				end//always
	
	finish:	begin// state
					count = count + 1'b1;
						if(count < 4'd4)
							begin//if
								nextState = a_b;
							end//if
						else
							begin//else
						nextState = finish;
							end//else
						end//state finish
		endcase		
end//always

always @ (posedge clk)
begin
		case(state)
		start: begin
				outA <= 4'd1;
				outB <= 4'd2;
				outC <= 4'd0;
				outD <= 4'd3;
		end
		
		a_b:	begin
				if(outA < outB)
				begin//if
					outA <= outB;
					outB <= outA;
				end//if
			else
			begin//else
				outA <= outA;
				outB <= outB;
			end//else
		end//a_b

		b_c:  begin
					if(outB < outC)
						begin//if
							outB <= outC;
							outC <= outB;
						end//if
					else
						begin//else
						outB <= outB;
						outC <= outC;
						end//else
					end//b_c

		c_d: begin
				if(outC < outD)
					begin//if
						outC <= outD;
						outD <= outC;
					end//if
				else
					begin//else
						outC <= outC;
						outD <= outD;
					end//else
					end//c_d
		//maybe put state final as the last case in the statement			
		endcase
	end
	
always @ (posedge clk)
	begin 
		case(outD) 
				4'h0: o1 = 7'b1000000;
				4'h1: o1 = 7'b1111001;
				4'h2: o1 = 7'b0100100;
				4'h3: o1 = 7'b0110000;
				4'h4: o1 = 7'b0011001;
				4'h5: o1 = 7'b0010010;
				4'h6: o1 = 7'b0000010;
				4'h7: o1 = 7'b1111000;
				4'h8: o1 = 7'b0000000;
				4'h9: o1 = 7'b0011000;
				4'hA: o1 = 7'b0001000;
				4'hB: o1 = 7'b0000011;
				4'hC: o1 = 7'b1000110;
				4'hD: o1 = 7'b0100001;
				4'hE: o1 = 7'b0000110;
				4'hF: o1 = 7'b0001110;
		endcase
		
		case(outC) 
				4'h0: o2 = 7'b1000000;
				4'h1: o2 = 7'b1111001;
				4'h2: o2 = 7'b0100100;
				4'h3: o2 = 7'b0110000;
				4'h4: o2 = 7'b0011001;
				4'h5: o2 = 7'b0010010;
				4'h6: o2 = 7'b0000010;
				4'h7: o2 = 7'b1111000;
				4'h8: o2 = 7'b0000000;
				4'h9: o2 = 7'b0011000;
				4'hA: o2 = 7'b0001000;
				4'hB: o2 = 7'b0000011;
				4'hC: o2 = 7'b1000110;
				4'hD: o2 = 7'b0100001;
				4'hE: o2 = 7'b0000110;
				4'hF: o2 = 7'b0001110;
		endcase
	
	case(outB) 
				4'h0: o3 = 7'b1000000;
				4'h1: o3 = 7'b1111001;
				4'h2: o3 = 7'b0100100;
				4'h3: o3 = 7'b0110000;
				4'h4: o3 = 7'b0011001;
				4'h5: o3 = 7'b0010010;
				4'h6: o3 = 7'b0000010;
				4'h7: o3 = 7'b1111000;
				4'h8: o3 = 7'b0000000;
				4'h9: o3 = 7'b0011000;
				4'hA: o3 = 7'b0001000;
				4'hB: o3 = 7'b0000011;
				4'hC: o3 = 7'b1000110;
				4'hD: o3 = 7'b0100001;
				4'hE: o3 = 7'b0000110;
				4'hF: o3 = 7'b0001110;
		endcase
	
	case(outA) 
				4'h0: o4 = 7'b1000000;
				4'h1: o4 = 7'b1111001;
				4'h2: o4 = 7'b0100100;
				4'h3: o4 = 7'b0110000;
				4'h4: o4 = 7'b0011001;
				4'h5: o4 = 7'b0010010;
				4'h6: o4 = 7'b0000010;
				4'h7: o4 = 7'b1111000;
				4'h8: o4 = 7'b0000000;
				4'h9: o4 = 7'b0011000;
				4'hA: o4 = 7'b0001000;
				4'hB: o4 = 7'b0000011;
				4'hC: o4 = 7'b1000110;
				4'hD: o4 = 7'b0100001;
				4'hE: o4 = 7'b0000110;
				4'hF: o4 = 7'b0001110;
		endcase
	end
endmodule
			//if the counter ==4 display the outputs else go back to state a_b